Design of Energy-Efficient Approximate Multiplier Architecture for Real-Time Image Processing Applications
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Abstract
This paper presents a novel energy-efficient approximate multiplier architecture specifically designed for real-time image processing applications. The rapid growth of multimedia systems and embedded vision platforms demands arithmetic units that balance computational accuracy with strict power and area constraints. The proposed design integrates a hybrid partial product truncation (PPT) technique with a novel approximate 4:2 compressor operating in a 45 nm CMOS technology node. By selectively approximating less-significant partial products and employing an error correction logic (ECL) module, the architecture achieves a superior accuracy–efficiency trade-off. Post-synthesis results demonstrate a 20.19% reduction in Power-Delay Product (PDP) and 41.6% improvement in delay compared to state-of-the-art designs. The multiplier is validated across benchmark image processing kernels—image sharpening, edge detection, and Discrete Cosine Transform (DCT)—achieving a Peak Signal-to-Noise Ratio (PSNR) of 46.8 dB and Structural Similarity Index (SSIM) of 0.994, confirming perceptual fidelity well within human visual tolerance. Comparative analysis against five leading approximate multiplier designs confirms the proposed architecture's superiority in energy efficiency without significant accuracy degradation.
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